1. Field of the Invention:
The present invention relates to digital frequency dividers. More specifically, the present invention relates to digital programmable frequency dividers.
While the present invention is described herein with reference to illustrative embodiments for particular applications, it should be understood that the invention is not limited thereto. Those having ordinary skill in the art and access to the teachings provided herein will recognize additional modifications, applications, and embodiments within the scope thereof and additional fields in which the present invention would be of significant utility.
2. Description of the Related Art:
Digitally programmable frequency dividers are utilized in a variety of digital signal processing applications. For example, conventional digital programmable frequency dividers are employed in phase locked loops included within high frequency digital communication systems. The bandwidth of the composite digital communication system is typically defined by the bandwidth of the phase locked loop. As the bandwidth of the phase locked loop is determined by the maximum operating frequency of the associated frequency divider, it follows that the bandwidth of the communication system is also determined thereby. Accordingly, increases in the speed (operating frequency) of digital frequency dividers allow for increases in the bandwidth of digital communication systems.
The speed of a digital frequency divider is determined by the number of gate delays within the critical path of the divider. The critical path of a digital circuit corresponds to the longest unclocked signal path included therein. The maximum speed of a digital frequency divider is typically inversely proportional to one half of the composite gate delay experienced by a signal traversing the critical path. Unfortunately, existing frequency divider circuits employing static flip-flops and other digital logic generally require four to eight complex (as opposed to simple inverting) gates in the critical path. Critical path delays of this duration limit the speed of digital dividers to less than desired values in advanced communication systems.
In applications requiring division by even integers, Johnson counters have been utilized in frequency dividers capable of operating at higher frequencies than conventional frequency dividers. A Johnson counter includes a ring of D-type flip-flops separated by transmission gates. The signal to be divided and the inverse thereof are applied to adjacent transmission gates and the frequency division ratio is determined by the number of flip-flops included within the ring. High speed Johnson counters operate at higher frequencies than conventional frequency dividers by utilizing dynamic D-type flip-flops. Nonetheless, digital signal processing in advanced communication systems typically necessitates frequency division by both even and odd integers.
Hence, a need in the art exists for a high speed digital programmable frequency divider capable of frequency division by even and odd integers.